1. Field of the Invention
The present invention relates to pulse generating circuits for use in semiconductor devices, and to a pulse generating circuit for use in a semiconductor device for generating a one shot pulse in accordance with change in the level of an address signal, such as an ATD circuit provided in a DRAM.
2. Description of the Background Art
FIG. 3 is a schematic block diagram showing a conventional DRAM. In FIG. 3, a row address is input into a row address buffer 21, and the input row address is decoded by a row decoder 22 to be applied to a memory cell array 23. When a RAS signal is applied to a control circuit 28, a row address of the memory cell array 23 is designated in the timing of the RAS signal. Meanwhile, a column address is externally input into a column address buffer 24 and applied to a column decoder 25, and an OR output of each address is applied to ATD circuit 27. The ATD circuit 27 upon detecting a change in the level of an address signal, generates a one shot pulse as an internal CAS signal and applies the same to the column decoder 25. The column decoder 25 decodes a column address signal and designates a column address of the memory cell array 23 through a sense amplifier 26. Externally input data is applied from an I/0 29 to the memory cell array 23 through the sense amplifier 26. If a R/W signal applied to the control circuit 28 indicates a state of writing, the data is written into a designated address of the memory cell array 23. If the R/W signal indicates a state of reading, an address of the memory cell array 23 is designated by a row address signal and a column address signal, data is read out from a corresponding address, and the read out data is amplified at the sense amplifier 26 and then output through the I/0 29.
FIG. 4 is a diagram of an electrical circuit showing one example of the ATD circuit shown in FIG. 3. Referring to FIG. 4, an address signal, for example, is input as a clock input .phi..sub.IN. The clock input .phi..sub.IN is input to the gate of a P type MOS transistor 2 and the gates of N type MOS transistors 8 and 10, and inverted at an inverter 1 to be applied as .phi..sub.IN to the gate of N type MOS transistor 5 and the gates of N type MOS transistors 12 and 14. A P type MOS transistor 3 is connected in parallel to a P type MOS transistor 2, a power supply voltage V.sub.cc is provided to the drains of the P type MOS transistors 2 and 3, the sources of the P type MOS transistors 2 and 3 are connected to the drain of the N type MOS transistor 8, an N type MOS transistor 9 is connected between the source of the N type MOS transistor 8 and the drain of the N type MOS transistor 10, and an N type MOS transistor 11 is connected between the source of the N type MOS transistor 10 and ground. Each gate of the P type MOS transistor 3 and the N type MOS transistors 9 and 11 is connected to a node N1.
A P type MOS transistor 4 is connected in parallel to a P type MOS transistor 5, a power supply voltage V.sub.cc is provided to the drains of the P type MOS transistors 4 and 5, the sources of the P type MOS transistors 4 and 5 are connected to the drain of an N type MOS transistor 12, an N type MOS transistor 13 is connected between the source of the N type MOS transistor 12 and the drain of the N type MOS transistor 14, and an N type MOS transistor 15 is connected between the source of the N type MOS transistor 14 and ground. Each gate of the P type MOS transistor 4, the N type MOS transistors 13 and 15 is connected to a node N2. The node N1 is connected to the connection point of the sources of the P type MOS transistors 4 and 5 and the drain of N type MOS transistor 12, while the node N2 is connected to the connection point of the sources of the P type MOS transistors 2 and 3 and the drain of the N type MOS transistor 8.
The gates of the P type MOS transistors 7 and 6 constituting a 2-input NAND circuit are connected to the nodes N1 and N2. The drains of the P type MOS transistors 6 and 7 are each provided with the power supply voltage V.sub.cc, the sources are connected together to be output as .phi..sub.OUT and also connected to the drain of an N type MOS transistor 17, the source of the N type MOS transistor 16 is connected to the drain of the N type MOS transistor 17, and the source of the N type MOS transistor 17 is grounded. The gate of the N type MOS transistor 16 is connected to the node N1, while the gate of the N type MOS transistor 17 is connected to the node N2.
FIG. 5 is a timing chart for use in illustration of an operation of the ATD circuit shown in FIG. 4. Now, referring to FIG. 5, a description of the operation of the ATD circuit shown in FIG. 4 follows. The N type MOS transistors 8-11 and 12-15 function as high resistance elements. As shown in FIG. 5(a), when the clock input .phi..sub.IN rises to an "H" level, the P type MOS transistor 2 is turned off, the N type MOS transistors 8 and 10 conduct, and .phi..sub.IN which is an output of the inverter 1 is pulled down to an "L" level. Accordingly, the P type MOS transistor 5 conducts, while the N type MOS transistors 12 and 14 are turned off. As a result, the node N1 is pulled to the "H" level, while the N type MOS transistors 9 and 11 conduct.
With the P type MOS transistors 2 and 3 being non-conductive, the node N2 attains the "L" level as shown in FIG. 5(d). At that time, as shown in FIG. 5(c), the node N2 rapidly rises from the "L" level to the "H" level, while the node N2 is pulled down to the "L" level from the "H" level gradually as shown in FIG. 5(d), since the N type MOS transistors 8-11 function as the high resistance elements. Therefore, the P type MOS transistor 7 has conducted before the node N1 rises to the "H" level, while the P type MOS transistor 6 conducts when the node N2 is pulled down to the "L" level. Therefore as shown in FIG. 5(e), a one shot pulse by which the sources of the P type MOS transistors 6 and 7 attain the "L" level only during a period T1 is output as .phi..sub.OUT.
Conversely, when the clock input .phi..sub.IN is pulled from the "H" level to the "L" level, the node N2 rapidly rises to the "H" level from the "L" level, and the node N.sub.1 is gradually pulled to the "L" level from the "H" level. As a result, a one shot pulse which attains the "L" level only during a period T2 is output as .phi..sub.OUT.
In the ATD circuit show in FIG. 4, as described above, it takes a longer period of time for .phi..sub.OUT to change its level from "L" to "H" in the case in which the node N2 changes its level from "H" to "L" as compared to the case in which the node N1 changes its level from the "H" to "L", resulting in different one shot pulse widths between T1 and T2. Accordingly, the ATD circuit shown in FIG. 4 suffers from a disadvantage that accessing time varies depending upon change in address when used for an SRAM or a DRAM.